1. Field of the Invention
The invention relates to cache systems used in computer systems, and more particularly to a write through third level cache system used with a write back second level cache system, the third level cache including caching of the shared or exclusive nature of the data.
2. Description of the Related Art
Computer systems are getting ever more powerful. Originally personal computers used a simple 8 and 16 bit microprocessor at a relatively slow clock rate. As the capabilities of the microprocessors and subsystems improved, so did system performance. 16 and 32 bit microprocessors were used and clock rates increased from 2 or 4.77 MHz to 66 MHz. Memory speeds increased, though not quite at the same rate as the performance increase in the microprocessors. To partially alleviate this lag, memory system architectures became more elaborate. Cache memory systems were used to bridge the speed gap. Eventually a cache system was integrated unto the microprocessor, with second level external cache systems being used in performance oriented cases. This use of cache systems improved system performance at some increase in complexity. However, the performance gains were still limited because of the fact that only one processor was present.
A second way to increase performance was to use multiple processors. Originally file servers and UNIX hosts used single processor personal computers. This was adequate in the beginning, but user performance demands required more. Ultimately multiprocessor units were developed. This partially resolved the problem of only one microprocessor but developed different problems. Originally the units were asymmetric, due to limitations in the various components, but later designs became symmetric. These symmetric multiprocessors (SMPs) became quite powerful. But as the microprocessors continued to increase in performance, the bus connecting the processors became a major limiting factor. The very high performance processors readily saturated the bus, so that adding another processor not only did not add performance, it might actually decrease performance. The bus limited the scalability of the system. Therefore yet another design limitation had been reached, limiting performance increases in the system. It is then clearly desirable to avoid this saturation of the common or host bus, allowing more processors to be added, improving the scalability and total performance of the computer system.